Phase-locked loops (“PLLs”) are commonly used to support the generation of sampling clocks for data recovery in high speed data transmission systems. “Bang-bang” PLLs are often utilized due to a nature of responses to the bang-bang PLLs' dual path architecture. Bang-bang PLLs may utilize two paths—an integral path and a proportional path. The integral path is generally a low-bandwidth path that is used to track the frequency of an incoming data stream. The proportional path is generally a high-bandwidth path (e.g., a higher bandwidth than the integral control path) that is used to track an optimum instantaneous sampling position of the incoming data stream. The integral and/or proportional control paths may be used to control an oscillator, such as a voltage-controlled oscillator (“VCO”) of a bang-bang PLL.
A device, such as an analog and/or digital receiver, may receive an input data stream. Due to various factors (e.g., line noise, lossiness, etc.), the phase of the input data stream may vary unpredictably. This phenomenon may be referred to as jitter. A PLL may be used to align a data sampling clock to the input data stream to assist in accounting for jitter in the data stream.